1. Field of the Invention
The present invention relates to a layout pattern decomposition method, and more particularly, to a layout pattern decomposition method for double patterning technique.
2. Description of the Prior Art
With rapid advancement of semiconductor fabricating technology, the integration level of integrated circuits (ICs) is bound to increase continuously in order to improve the device speed and performance and comply with current requirements for lightweight, slimness, and compactness. Improvement of the integration level is inevitably relies on reducing size of feature patterns and pitches between features patterns which construct the devices and ICs. However, size and/or pitch reduction increases difficulty and complexity of device productions and suffers limitations in the prior art.
For example, lithography beyond the 45 nm node faces numerous challenges. The challenges are associated with the use of photoresists to define sub-40 nm features, including line-edge roughness, shot noise, acid diffusion blur, and resist collapse. As a countermeasure against to those problems, there have been proposed multi patterning technique and double patterning technique. In the double patterning technique, the features of a given target pattern are decomposed/separated into two different colors and masks, and then imaged separately to form the desired pattern which includes the original given target pattern in an objective layer.
Accordingly, it is an imperative issue to efficaciously decompose and separate one given target feature pattern into two masks and to successfully form the original given feature pattern by double patterning technique.